The present invention relates to a clock signal supplying apparatus and particularly, a clock signal supplying apparatus for supplying a clock signal to a plurality of functional blocks in a serial data processing switch system such as a switchboard in asynchronous transfer mode communications (referred to as ATM hereinafter).
As the frequency of a clock signal for electronic devices has sharply been increased for carrying out high-quality high-speed processing, its relevant problems arise including fault action of an electronic device due to clock noise and increase of power consumption For attenuating the noise or minimizing the power consumption, a clock signal control technique is employed in which the functional blocks in an electronic apparatus are supplied with clock signals only when they are carrying out logic operations.
For example, a logic circuit driving apparatus for supplying a clock signal at timing with the action of a functional block is depicted in Japanese Patent Laid-open Publication No. H4-302014. The logic circuit driving apparatus includes functional blocks 1, 2, and 3 for carrying out a series of logic operations, as shown in FIG. 4. The functional block 1 is supplied with an action data signal 4a, starts performing an operation, and delivers an action data signal 4b during the operation. The functional block 2 is responsive to the action data signal 4b for starting a logic operation and releases an action data signal 4c during the logic operation. The action data signal 4c is then supplied to the functional block 3 which in turn starts its logic operation.
The logic circuit driving apparatus also includes a sequence controller 5 to which status data signals 6a, 6b, and 6c are fed from their respective functional blocks 1, 2, and 3. Also, a master clock signal 7 is supplied to the sequence controller 5. In response to the status data signals 6a, 6b, and 6c, the sequence controller 5 produces and delivers action signals 8a, 8b, and 8c, each consisting of a clock signal CLK and other signals, to the functional blocks 1, 2, and 3 respectively. The functional blocks 1, 2, and 3 are also loaded with a common reset signal 9.
In action, when the action data signal 4a is not supplied to the logic circuit driving apparatus, the functional block 1 remains disabled releasing none of the action data signal 4b and the status data signal 6a. Accordingly, the functional block 1 is disabled to receive the action signal 8a thus the clock signal CLK from the sequence controller 5. Equally, the functional blocks 2 and 3 are not supplied with the action data signals 4b and 4c and thus receive none of the clock signal CLK.
Upon receiving the action data signal 4a , the functional block 1 starts with delivering the status data signal 6a to the sequence controller 5. The sequence controller 5 in response to the status data signal 6a releases the action signal 8a to the functional block 1. The functional block 1 receives the clock signal CLK in the action signal 8a and then performs its logic operation. During the logic operation, the functional block 1 delivers the action data signal 4b to the functional block 2. Upon receiving the action data signal 4b, the functional block 2 starts with the same action as of the functional block 1.
In this manner, the functional blocks 1 and 2 supply the succeeding functional blocks 2 and 3 with their respective action data signals 4b and 4c. The functional blocks 1, 2, and 3 excited by the action data signals 4a, 4b, and 4c respectively deliver their respective status data signals 6a, 6b, and 6c to the sequence controller 5 and in turn receive the clock signal CLK from the sequence controller 5 for performing their logic operations.
Such a conventional logic circuit driving apparatus has a disadvantage to be solved. Since the functional block 1 to 3 start operating only when they have been loaded with the action data signals 4a to 4c, they have to be programmed to operate in a time sequence and thus, are hardly suited for any applicable system.
For example, in a specific system such as an ATM switchboard which has to carry out actions in response to received data without using the action data signal 4a, the functional blocks are activated in different orders depending on the received data. The prescribed conventional logic circuit driving apparatus may hardly be utilized for effective control of the clock signal.